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ltc4306 1 4306f the ltc ? 4306 is a 4-channel, 2-wire bus multiplexer with bus buffers to provide capacitive isolation between the upstream bus and downstream buses. through software control, the ltc4306 connects the upstream 2-wire bus to any desired combination of downstream buses. each channel can be pulled up to a supply voltage ranging from 2.2v to 5.5v, independent of the ltc4306 supply voltage. the downstream channels are also provided with alert1-alert4 inputs for fault reporting. programmable timeout circuitry disconnects the down- stream buses if the bus is stuck low. when activated, rise time accelerators source currents into the 2-wire bus pins to reduce rise time. driving the enable pin low restores all features to their default states. three address pins provide 27 distinct addresses. the ltc4306 is available in 24-lead qfn (4mm 5mm) and ssop packages. nested addressing 5v/3.3v level translator capacitance buffer/bus extender 1:4 2-wire multiplexer/switch connect sda and scl lines with 2-wire bus commands supply independent bidirectional buffer for sda and scl lines increases fan-out programmable disconnect from stuck bus compatible with i 2 c and smbus standards rise time accelerator circuitry smbus compatible alert response protocol two general purpose inputs-outputs prevents sda and scl corruption during live board insertion and removal from backplane 10kv human body model esd ruggedness 24-lead qfn (4mm 5mm) and ssop packages 4-channel, 2-wire bus multiplexer with capacitance buffering features descriptio u applicatio s u typical applicatio u , ltc and lt are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. patent pending. v cc 0.01 f 3.3v ? ? ? 2.5v 5v 10k ltc4306 address = 1000 100 address = 1111 000 address = 1111 000 scl1 sda1 alert1 sclin sdain alert scl4 sda4 alert4 adr2 adr1 adr0 gnd sfp module 1 micro- controller 10k 10k 10k 10k 10k 10k sfp module 4 10k 10k 4306 ta01a a level shifting and nested addressing application 4306 ta01b v cc = 3.3v vcard1 = 3.3v vcard4 = 5v vback = 2.5v scl4 2v/div 500ns/div scl1 2v/div sclin 2v/div i 2 c bus waveforms
ltc4306 4306f 2 (note 1) supply voltage (v cc ) ................................... C0.3v to 7v input voltages (adr0, adr1, adr2, enable, alert1, alert2, alert3, alert4) .................................................. C0.3v to 7v output voltages (alert, ready) ............... C0.3v to 7v input/output voltages (sdain, sclin, scl1, sda1, scl2, sda2, scl3, sda3, scl4, sda4, gpio1, gpio2) ........ C0.3v to 7v output sink currents (sdain, sclin, scl1-4, sda1-4, gpi01-2, alert, ready) ..................................... 10ma operating temperature range ltc4306c ............................................... 0 c to 70 c ltc4306i ............................................. C40 c to 85 c storage temperature range ssop ................................................. C65 c to 150 c qfn ................................................... C65 c to 125 c lead temperature (soldering, 10 sec) ssop ................................................................ 300 c order part number consult ltc marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a label on the shipping container. ltc4306cufd LTC4306IUFD exposed pad (pin 25), pcb connection optional must be connected to the pcb to obtain ja = 43 c/w otherwise ja = 140 c/w. t jmax = 125 c uf part marking* 4306 package/order i for atio uu w order part number ltc4306cgn ltc4306ign t jmax = 125 c, ja = 85 c/w 1 2 3 4 5 6 7 8 9 10 11 12 top view gn package 24-lead plastic ssop 24 23 22 21 20 19 18 17 16 15 14 13 scl3 sda3 alert sdain gnd sclin enable v cc alert4 gpi01 gpi02 adr0 alert2 scl2 sda2 alert3 alert1 sda1 scl1 scl4 sda4 ready adr2 adr1 8 9 top view 25 ufd package 24-lead (4mm 5mm) plastic qfn 10 11 12 24 23 22 21 20 6 5 4 3 2 1 alert sdain gnd sclin enable v cc alert4 alert3 alert1 sda1 scl1 scl4 sda4 ready sda3 scl3 alert2 scl2 sda2 gpio1 gpi02 adr0 adr1 adr2 7 14 15 16 17 18 19 13 absolute axi u rati gs w ww u order options tape and reel: add #tr lead free: add #pbf lead free tape and reel: add #trpbf lead free part marking: http://www.linear.com/leadfree/ the denotes specifications which apply over the full specified temperature range, otherwise specifications are at t a = 25 c. v cc = 3.3v unless otherwise noted. symbol parameter conditions min typ max units power supply/start-up v cc input supply range 2.7 5.5 v i cc input supply current downstream connected, scl bus low, 5.2 8 ma sda bus high, v cc = 5.5v i cc enable = 0v input supply current v enable = 0v, v cc = 5.5v 1.25 2.5 ma v uvlou uvlo upper threshold voltage 2.3 2.5 2.7 v electrical characteristics
ltc4306 3 4306f the denotes specifications which apply over the full specified temperature range, otherwise specifications are at t a = 25 c. v cc = 3.3v unless otherwise noted. electrical characteristics symbol parameter conditions min typ max units v uvlohyst uvlo threshold hysteresis voltage 100 175 250 mv v th en enable falling threshold voltage 0.8 1.0 1.2 v v enhyst enable threshold hysteresis voltage 60 mv t phlen enable delay, on-off 60 ns t plhen enable delay, off-on 20 ns i inen enable input leakage current v enable = 0v, 5.5v, v cc = 5.5v 0 1 a v lowready ready pin logic low output voltage i pull-up = 3ma, v cc = 2.7v 0.18 0.4 v i offready ready off state input leakage current v ready = 0v, 5.5v, v cc = 5.5v 0 1 a upstream-downstream buffers v os,buf buffer offset voltage r bus = 10k, v cc = 2.7v, 5.5v (note 4) 25 60 100 mv v os,up-buf upstream buffer offset voltage v cc = 2.7v, r bus = 2.7k (note 4) 40 80 120 mv v in, buffer = 0v v cc = 5.5v, r bus = 2.7k (note 4) 70 110 150 mv v os,down-buf downstream buffer offset voltage v cc = 2.7v, r bus = 2.7k (note 4) 60 110 160 mv v in, buffer = 0v v cc = 5.5v, r bus = 2.7k (note 4) 80 140 200 mv v ol output low voltage, v in,buffer = 0v sda, scl pins; i sink = 4ma, 400 mv v cc = 3v, 5.5v output low voltage, v in,buffer = 0.2v sda, scl pins; i sink = 500 a, 320 mv v cc = 2.7v, 5.5v v il,max buffer input logic low voltage v cc = 2.7v, 5.5v 0.4 0.52 0.64 v v thsda,scl downstream sda, scl logic threshold voltage 0.8 1.0 1.2 v i leak input leakage current sda, scl pins; v cc = 0v to 5.5v; 0 5 a buffers inactive rise time accelerators v sda,scl slew minimum slew requirement to activate sdain, sclin, sda1-4, scl1-4 pins 0.4 0.8 v/ s rise time accelerator currents v rise,dc rise time accelerator dc threshold voltage sdain, sclin, sda1-4, scl1-4 pins 0.7 0.8 1 v i boost rise time accelerator pull-up current sdain, sclin, sda1-4, scl1-4 pins 4 5.5 ma (note 3) gpios v gpio(th) gpio pin input threshold 0.8 1 1.2 v v gpio(ol) gpio pin output low voltage i gpio = 5ma, v cc = 2.7v 0.2 0.4 v v gpio(oh) gpio pin output high voltage i gpio = C200 a, v cc = 2.7v v cc C 0.3 v i gpio(in) gpio pin input leakage current v gpio = 0v, 5.5v, v cc = 5.5v 0 1 a stuck low timeout circuitry v timer(l) stuck low falling threshold voltage v cc = 2.7v, 5.5v 0.4 0.52 0.64 v v timer(hyst) stuck low threshold hysteresis voltage 80 mv t timer1 timeout time #1 timset1,0 = 01 25 30 35 ms t timer2 timeout time #2 timset1,0 = 10 12.5 15 17.5 ms t timer3 timeout time #3 timset1,0 = 11 6.25 7.5 8.75 ms alert v alert(ol) alert output low voltage i alert = 3ma, v cc = 2.7v 0.2 0.4 v i off,alert alert off state input leakage current v alert = 0v, 5.5v 0 1 a i in,alert1-4 alert1-alert4 input current v alert1-4 = 0v, 5.5v 0 1 a
ltc4306 4306f 4 the denotes specifications which apply over the full specified temperature range, otherwise specifications are at t a = 25 c. v cc = 3.3v unless otherwise noted. note 1: absolute maximum ratings are those values beyond which the life of a device may be impaired. note 2: guaranteed by design and not subject to test. note 3: the boosted pull-up currents are regulated to prevent excessively fast edges for light loads. see the typical performance characteristics for rise time as a function of v cc and parasitic bus capacitance c bus and for i boost as a function of v cc and temperature. note 4: when a logic low voltage, v low , is forced on one side of the upstream-downstream buffers, the voltage on the other side is regulated to a voltage v low2 = v low + v os , where v os is a positive offset voltage. v os,up-buf is the offset voltage when the ltc4306 is driving the upstream pin (e.g., sdain) and v os,down-buf is the offset voltage when the ltc4306 is driving the downstream pin (e.g., sda1). see the typical performance characteristics for v os,up-buf and v os,down-buf as a function of v cc and bus pull-up current. note 5: when floating, the adr0-adr2 pins can tolerate pin leakage currents up to i adr(float) and still convert the address correctly. electrical characteristics symbol parameter conditions min typ max units v alert1-4(in) alert1-alert4 pin input falling 0.8 1.0 1.2 v threshold voltages v alert1-4(hy) alert1-alert4 pin input threshold 80 mv hysteresis voltages i 2 c interface v adr(h) adr0-2 input high voltage 0.75 ? v cc 0.9 ? v cc v v adr(l) adr0-2 input low voltage 0.1 ? v cc 0.25 ? v cc v i adr(in, l) adr0-2 logic low input current adr0-2 = 0v, v cc = 5.5v C30 C60 C80 a i adr(float) adro-2 allowed input current v cc = 2.7v, 5.5v (note 5) 5 13 a i adr(in, h) adr0-2 logic high input current adr0-2 = v cc = 5.5v 30 60 80 a v sdain,sclin(th) sdain, sclin input falling threshold v cc = 5.5v 1.4 1.6 1.8 v voltages v sdain,sclin(hy) sdain, sclin hysteresis 30 mv i sdain,sclin(oh) sdain, sclin input current scl, sda = v cc 0 5 a c in sda, scl input capacitance (note 2) 6 pf v sdain(ol) sdain output low voltage i sda = 4ma, v cc = 2.7v 0.2 0.4 v i 2 c interface timing f scl maximum scl clock frequency (note 2) 400 khz t buf bus free time between stop/start condition (note 2) 0.75 1.3 s t hd,sta hold time after (repeated) start condition (note 2) 45 100 ns t su,sta repeated start condition set-up time (note 2) C30 0 ns t su,sto stop condition set-up time (note 2) C30 0 ns t hd,dati data hold time input (note 2) C25 0 ns t hd,dato data hold time output (note 2) 300 600 900 ns t su,dat data set-up time (note 2) 50 100 ns t f scl, sda fall times (note 2) 20 + 0.1 ? 300 ns c bus t sp pulse width of spikes suppressed by the (note 2) 50 150 250 ns input filter
ltc4306 5 4306f rise time vs c bus vs v cc buffer circuitry t phl vs temperature i cc vs temperature v os,up-buf vs bus pull-up current typical perfor a ce characteristics uw temperature ( c) C50 t phl (ns) 80 100 120 25 75 4306 g01 60 40 C25 0 50 100 125 20 0 v cc = 3.3v v cc = 5v capacitance, c bus (pf) 0 rise time (ns) 150 200 250 800 4306 g02 100 50 0 200 400 600 1000 v cc = 3.3v v cc = 5v dv = 0.3v ? v cc to 0.7v ? v cc r bus = 10k temperature ( c) C50 current (ma) 4 5 6 25 75 4306 g03 3 2 C25 0 50 100 125 1 0 v cc = 3.3v v cc = 5v upstream connected to channel 1, scl bus low, sda bus high bus pull-up current (ma) 1 0 v os (mv) 100 120 140 4306 g04 80 60 0 2 3 4 40 20 180 160 v cc = 3.3v v cc = 5v v os,down-buf vs bus pull-up current bus pull-up current (ma) 0 0 v os (mv) 50 100 150 200 250 300 12 34 4306 g05 v cc = 3.3v v cc = 5v downstream r fet on resistance vs v cc and temperature temperature ( c) C50 0 r on ( ? ) 5 15 20 25 50 45 4306 g06 10 0 C25 75 100 25 125 30 35 40 v cc = 3.3v v cc = 5v (t a = 25 c, unless otherwise indicated) i boost vs temperature temperature ( c) C50 8 10 14 25 75 4306 g07 6 4 C25 0 50 100 125 2 0 12 i boost (ma) v cc = 5v v cc = 3.3v
ltc4306 4306f 6 uu u pi fu ctio s (gn24 package/ufd24 package) alert (pin 3/pin 1): fault alert output. an open-drain output that is pulled low when a fault occurs to alert the host controller. the ltc4306 pulls alert low when any of the alert1-alert4 pins is low, when the 2-wire bus is stuck low, or when the connection requirement bit of register 2 is low and a master tries to connect to a downstream channel that is low. see operation section for the details of how alert is set and cleared. the ltc4306 is compatible with the smbus alert response address protocol. connect a 10k resistor to a power supply voltage to provide the pull-up. tie to ground if unused. sdain (pin 4/pin 2): serial bus data input and output. connect this pin to the sda line on the master side. an external pull-up resistor or current source is required. gnd (pin 5/pin 3): device ground. sclin (pin 6/pin 4): serial bus clock input. connect this pin to the scl line on the master side. an external pull-up resistor or current source is required. enable (pin 7/pin 5): digital interface enable and regis- ter reset. driving enable high enables i 2 c communica- tion to the ltc4306. driving this pin low disables i 2 c communication to the ltc4306 and resets the registers to their default state as shown in the operation section. when enable returns high, masters can read and write the ltc4306 again. if unused, tie enable to v cc . v cc (pin 8/pin 6): power supply voltage. connect a bypass capacitor of at least 0.01 f directly between v cc and gnd for best results. gpio1-gpio2 (pins 10, 11/pins 8, 9): general purpose input/output. these two pins can be used as logic inputs, open-drain outputs or push-pull outputs. the n-channel mosfet pull-down devices are capable of driving leds. when used in input or open-drain output mode, the gpios can be pulled up to a supply voltage ranging from 1.5v to 5.5v independent of the v cc voltage. gpios default to a high impedance open-drain output mode. there are gpio configuration and status bits in register 1 and register 2. float if unused. adr0-adr2 (pins 12, 13, 14/pins 10, 11, 12): three- state serial bus address inputs. each pin may be floated, tied to ground or tied to v cc . there are therefore 27 possible addresses. see table 1 in applications informa- tion. when the pins are floated, they can tolerate 5 a of leakage current and still convert the address correctly. ready (pin 15/pin 13): connection ready digital output. an n-channel mosfet open-drain output transistor that pulls down when none of the downstream channels is connected to the upstream bus and turns off when one or more downstream channels is connected to the upstream bus. connect a 10k resistor to a power supply voltage to provide the pull-up. tie to ground if unused. scl1-scl4 (pins 18, 23, 1, 17/pins 16, 21, 23, 15): serial bus clock outputs channels 1-4. connect pins scl1-scl4 to the scl lines on the downstream channels 1-4, respectively. it is acceptable to float any pin that will never be connected to the upstream bus. other- wise, an external pull-up resistor or current source is required on each pin. sda1-sda4 (pins 19, 22, 2, 16/pins 17, 20, 24, 14): serial bus data output channels 1-4. connect pins sda1-sda4 to the sda lines on downstream channels 1-4, respectively. it is acceptable to float any pin that will never be connected to the upstream bus. otherwise, an external pull-up resistor or current source is required on each pin. alert1-alert4 (pins 20, 24, 21, 9/pins 18, 22, 19, 7): fault alert inputs, channels 1-4. devices on each of the four output channels can pull their respective pin low to indicate that a fault has occurred. the ltc4306 then pulls the alert low to pass the fault indication on to the host. see operation section below for the details of how alert is set and cleared. connect unused fault alert inputs to v cc . exposed pad (pin 25, ufd package only): power ground. exposed pad may be left open or connected to device ground.
ltc4306 7 4306f block diagra w + C + C sdain inacc slew rate detector outacc slew rate detector upstream downstream buffers sclin ready v cc inacc slew rate detector outacc slew rate detector 2-wire digital interface and registers stuck low 0.52v comparators upstream downstream buffers fet4 fet3 fet2 fet1 downstream 1v threshold comparators 4 4 4 5 uvlo sda1 sda2 sda3 sda4 scl1 scl2 scl3 scl4 alert1 alert2 alert3 alert4 alert conn fet1-fet4 timset1 timeout_real timeout_latch address fixed bits 10 inacc outacc failconn_attempt 1.6v/1.52v sclin sdain 100ns glitch filter 100ns glitch filter stuck low timeout circuitry connection circuitry 1 s filter v cc porb uvlo 50k 2pf + C + C + C enable gpio2 2.5v/2.35v 1.1v/1v 1v v cc + C gpio1 1v v cc 4 4 timset0 ch1conn-ch4conn 4 4 5 bus1_log-bus4_log i 2 c addr conn_req al1-al4 alert 1v threshold comparators 1 of 27 alert logic fet1-fet4 al1-al4 gnd adr2 adr1 adr0
ltc4306 4306f 8 control register bit definitions operatio u register 0 (00h) bit name type* description d7 downstream r indicates if upstream bus is connected connected to any downstream buses 0 = upstream bus disconnected from all downstream buses 1 = upstream bus connected to one or more downstream buses d6 alert1 logic state r logic state of alert1 pin, noninverting d5 alert2 logic state r logic state of alert2 pin, noninverting d4 alert3 logic state r logic state of alert3 pin, noninverting d3 alert4 logic state r logic state of alert4 pin, noninverting d2 failed connection r indicates if an attempt to connect to a attempt downstream bus failed because the connection requirement bit in register 2 was low and the downstream bus was low 0 = failed connection attempt occurred 1 = no failed attempts at connection occurred d1 latched timeout r latched bit indicating if a timeout has occurred and has not yet been cleared. 0 = no latched timeout 1 = latched timeout d0 timeout real time r indicates real-time status of stuck low timeout circuitry 0 = no timeout is occurring 1 = timeout is occurring note: masters write to register 0 to reset the fault circuitry after a fault has occurred and been resolved. because register 0 is read-only, no other functionality is affected. * for type, r/w = read write, r = read only register 1 (01h) bit name type* description d7 upstream r/w activates upstream rise time accelerators accelerator currents enable 0 = upstream rise time accelerator currents inactive (default) 1 = upstream rise time accelerator currents active d6 downstream r/w activates downstream rise time accelerators accelerator currents enable 0 = downstream rise time accelerator currents inactive (default) 1 = downstream rise time accelerator currents active d5 gpio1 output r/w gpio1 output driver state, driver state noninverting, default = 1 d4 gpio2 output r/w gpio2 output driver state, driver state noninverting, default = 1 d3-d2 reserved r not used d1 gpio1 logic r logic state of gpio1 pin, state noninverting d0 gpio2 logic r logic state of gpio2 pin, state noninverting * for type, r/w = read write, r = read only
ltc4306 9 4306f register 2 (02h) bit name type* description d7 gpio1 mode r/w configures input/output mode of configure gpio1 0 = output mode (default) 1 = input mode d6 gpio2 mode r/w configures input/output mode of configure gpio2 0 = output mode (default) 1 = input mode d5 connection r/w sets logic requirements for requirement downstream buses to be connected to upstream bus 0 = bus logic state bits (see register 3) of buses to be connected must be high for connection to occur (default) 1 = connect regardless of downstream logic state d4 gpio1 output r/w configures gpio1 output mode mode configure 0 = open-drain pull-down (default) 1 = push-pull d3 gpio2 output r/w configures gpio2 output mode mode configure 0 = open-drain pull-down (default) 1 = push-pull d2 mass write enable r/w enable mass write address using address (1011 101)b 0 = disable mass write 1 = enable mass write (default) d1 timeout mode bit 1 r/w stuck low timeout set bit 1** d0 timeout mode bit 0 r/w stuck low timeout set bit 0** * for type, r/w = read write, r = read only **stuck bus program table timset1 timset0 timeout mode 0 0 timeout disabled (default) 0 1 timeout after 30ms 1 0 timeout after 15ms 1 1 timeout after 7.5ms operatio u register 3 (03h) bit name type* description d7 bus 1 fet state r/w sets and indicates state of fet switches connected to downstream bus 1 0 = switch open (default) 1 = switch closed d6 bus 2 fet state r/w sets and indicates state of fet switches connected to downstream bus 2 0 = switch open (default) 1 = switch closed d5 bus 3 fet state r/w sets and indicates state of fet switches connected to downstream bus 3 0 = switch open (default) 1 = switch closed d4 bus 4 fet state r/w sets and indicates state of fet switches connected to downstream bus 4 0 = switch open (default) 1 = switch closed d3 bus 1 logic state r indicates logic state of downstream bus 1; only valid when disconnected from upstream bus ? 0 = sda1, scl1 or both are below 1v 1 = sda1 and scl1 are both above 1v d2 bus 2 logic state r indicates logic state of downstream bus 2; only valid when disconnected from upstream bus ? 0 = sda2, scl2 or both are below 1v 1 = sda2 and scl2 are both above 1v d1 bus 3 logic state r indicates logic state of downstream bus 3; only valid when disconnected from upstream bus ? 0 = sda3, scl3 or both are below 1v 1 = sda3 and scl3 are both above 1v d0 bus 4 logic state r indicates logic state of downstream bus 4; only valid when disconnected from upstream bus ? 0 = sda4, scl4 or both are below 1v 1 = sda4 and scl4 are both above 1v * for type, r/w = read write, r = read only ? these bits give the logic state of disconnected downstream buses to the master, so that the master can choose not to connect to a low downstream bus. a given bit is a dont care if its associated downstream bus is already connected to the upstream bus.
ltc4306 4306f 10 the ltc4306 is a 4-channel, 2-wire bus multiplexer/ switch with bus buffers to provide capacitive isolation between the upstream bus and downstream buses. mas- ters on the upstream 2-wire bus (sdain and sclin) can command the ltc4306 to any combination of the 4 downstream buses. masters can also program the ltc4306 to disconnect the upstream bus from the downstream buses if the bus is stuck low. undervoltage lockout (uvlo) and enable functionality the ltc4306 contains undervoltage lockout circuitry that maintains all of its sda, scl, gpio and alert pins in high impedance states until the device has sufficient v cc supply voltage to function properly. it also ignores any attempts to communicate with it via the 2-wire buses in this condi- tion. when the enable pin voltage is low (below 0.8v), all control bits are reset to their default high impedance states, and the ltc4306 ignores 2-wire bus commands. however, with enable low, the ltc4306 still monitors the alert1-alert4 pin voltages and pulls the alert pin low if any of alert1-alert4 is low. when enable is high, devices can read from and write to the ltc4306. connection circuitry masters on the upstream sdain/sclin bus can write to the bus 1 fet state through bus 4 fet state bits of register 3 to connect to any combination of downstream channels 1 to 4. by default, the connection circuitry shown in the block diagram will only connect to downstream channels whose corresponding bus logic state bits in register 3 are high at the moment that it receives the connection com- mand. if the ltc4306 is commanded to connect to mul- tiple channels at once, it will only connect to the channels that are high. masters can override this feature by setting the connection requirement bit of register 2 high. with this bit high, the ltc4306 executes connection com- mands without regard to the logic states of the down- stream channels. upon receiving the connection command, the connec- tion circuitry will activate the upstream-downstream buffers under two conditions: first, the master must be commanding connection to one or more downstream channels, and second, there must be no stuck low condition (see stuck low timeout fault discussion). if the connection command is successful, the upstream- downstream buffers pass signals between the upstream bus and the connected downstream buses. the ltc4306 also turns off its n-channel mosfet open-drain pull- down on the ready pin, so that ready can be pulled high by its external pull-up resistor. upstream-downstream buffers once the upstream-downstream buffers are activated, the functionality of the sdain and any connected down- stream sda pins is identical. a low forced on any con- nected sda pin at any time results in all pins being low. external devices must pull the pin voltages below 0.4v worst-case with respect to the ltc4306? ground pin to ensure proper operation. the sda pins enter a logic high state only when all devices on all connected sda pins force a high. the same is true for sclin and the connected downstream scl pins. this important feature ensures that clock stretching, clock arbitration and the acknowl- edge protocol always work, regardless of how the devices in the system are connected to the ltc4306. the upstream-downstream buffers provide capacitive isolation between sdain/sclin and the downstream con- nected buses. note that there is no capacitive isolation between connected downstream buses; they are only separated by the series combination of their switches on resistances. while any combination of downstream buses may be connected at the same time, logic high levels are corrupted if multiple downstream buses are active and both the v cc voltage and one or more downstream bus pull-up voltages are larger than the pull-up supply voltage for another downsteam bus. an example of this issue is shown in figure 1. during logic highs, dc current flows from v bus1 through the series combination of r1, n1, n2 and r2 and into v bus2 , causing the sda1 voltage to drop and current to be sourced into v bus2 . to avoid this problem, do not activate bus 1 or any other downstream bus whose pull- up voltage is above 2.5v when bus 2 is active. operatio u
ltc4306 11 4306f rise time accelerators the upstream accelerators enable and downstream ac- celerators enable bits of register 1 activate the upstream and downstream rise time accelerators, respectively. when activated, the accelerators turn on in a controlled manner and source current into the pins during positive bus transitions. when no downstream buses are connected, an upstream accelerator turns on when its pin voltage exceeds 0.8v and is rising at a minimum slew rate of 0.8v/ s. when one or more downstream buses are connected, the accelera- tor on a given pin turns on when these conditions are met: first, the pins voltage is rising at a minimum slew rate of 0.8v/ s; second, the voltages on both the upstream bus and the connected downstream buses exceed 0.8v. note that a downstream buss switch must be closed in order for its rise time accelerator current to be active. see the applications section for choosing a bus pull-up resis- tor value to ensure that the rise time accelerator switches turn on. do not activate boost currents on a bus whose pull-up supply voltage v bus is less than v cc . doing so would cause the boost currents to source current from v cc into the v bus supply during rising edges. downstream bus connection fault by default, the ltc4306 will only connect to downstream channels whose sda and scl pins are both high (above 1v) at the moment that it receives the connection com- mand. in this case, the ltc4306 sets the failed connec- tion attempt bit of register 0 low and pulls the alert pin low when the master tries to connect to a low downstream channel. note that users can write a high to the connection requirement bit of register 2 high to program the ltc4306 to connect to downstream channels regardless of their logic state at the moment of connection. in this case, the downstream channel connection fault never occurs. stuck low timeout fault the stuck low timeout circuitry monitors the two common internal nodes of the downstream sda and scl switches and runs a timer whenever either of the internal node voltages is below 0.52v. the timer is reset whenever both internal node voltages are above 0.6v. if the timer ever reaches the time programmed by timeout mode bits 1 and 0 of register 2, the ltc4306 pulls alert low and discon- nects the downstream bus(es) from the upstream bus by de-biasing the upstream-downstream buffers. note that the downstream switches remain in their existing state. the timeout real-time bit of register 0 indicates the real- time status of the stuck low situation. the latched timeout bit of register 0 is a latched bit that is set high when a timeout occurs. external faults on the downstream channels when a slave on downstream bus 1 pulls the alert1 pin below 1v, the ltc4306 passes this information to the master on the upstream bus by pulling the alert pin low. the same is true for the other three downstream buses. each bus has its own dedicated fault bit in register 0, so that masters can read register 0 to determine which buses have faults. alert functionality and fault resolution when a fault occurs, the ltc4306 pulls the alert pin low, as described previously. the procedure for resolving faults depends on the type of fault. if a master on the upstream bus is communicating with devices on a down- stream bus via the upstream-downstream buffer cir- cuitrychannel 1, for exampleand a device on this bus pulls the alert1 pin low, the ltc4306 acts transparently, and the master communicates directly with the device that caused the fault via the upstream-downstream buffer circuitry to resolve the fault. operatio u sda1 n1 n2 4306 f01 sda2 v cc = v bus1 = 5v v bus2 = 2.5v r1 10k r2 10k figure 1. example of unacceptable level shifting
ltc4306 4306f 12 in all other cases, the ltc4306 communicates with the master to resolve the fault. after the master broadcasts the alert response address (ara), the ltc4306 will respond with its address on the sdain line and release the alert pin. the alert line will also be released if the ltc4306 is addressed by the master. the alert signal will not be pulled low again until a different type of fault has occurred or the original fault is cleared and it occurs again. figure 2 shows the details of how the alert pin is set and reset. the downstream bus connection fault and faults that occur on unconnected downstream buses are grouped together and generate a single signal to drive alert. the stuck low timeout fault has its own dedicated pathway to alert; however, once a stuck low occurs, another one will not occur until the first one is cleared. for these reasons, once the master has established the ltc4306 as the source of the fault, it should read register 0 to determine the specific problem, take action to solve the problem, and clear the fault promptly. all faults are cleared by writing a dummy data byte to register 0, which is a read-only register. for example, assume that a fault occurs, the master sends out the ara, and the ltc4306 successfully writes its address onto sdain and releases its alert pin. the master reads register 0 and learns that the alert2 logic state bit is low. the master now knows that a device on downstream bus 2 has a fault and writes to register 3 to connect to bus 2, so that it can communicate with the source of the fault. at this point, the master writes to register 0 to clear the ltc4306 fault register. i 2 c device addressing twenty-seven distinct bus addresses are configurable using the three state adr0, adr1 and adr2 pins. table 1 shows the correspondence between pin states and ad- dresses. note that address bits a6 and a5 are internally configured to 1 and 0 respectively. in addition, the ltc4306 responds to two special addresses. address (1011 101) is a mass write used to write all ltc4306s, regardless of their individual address settings. the mass write can be masked by setting the mass write enable bit of register 2 to zero. address (0001 100) is the smbus alert response address. figure 3 shows data transfer over a 2-wire bus. supported commands users must write to the ltc4306 using the smbus write byte protocol and read from it using the read byte protocol. during fault resolution, the ltc4306 also supports the alert response address protocol. the formats for these protocols are shown in figure 4. users must follow the write byte protocol exactly to write to the ltc4306; if a repeated start condition is issued before a stop condition, the ltc4306 ignores the attempted write, and its control bits remain in their preexisting state. when operatio u d 4306 f02 v cc q write register 0 r d d fault on connected downstream bus v cc q write register 0 fault on disconnected downstream bus downstream bus connection fault address ltc4306 stuck bus ltc4306 responds to ara r d alert figure 2. setting and resetting the alert pin
ltc4306 13 4306f operatio u table 1. ltc4306 i 2 c device addressing hex device ltc4306 description address binary device address address pins h a6 a5 a4 a3 a2 a1 a0 r/w adr2 adr1 adr0 mass write ba 1 0 1 1 1 0 1 0 x x x alert response 19 0 0 0 1 1 0 0 1 x x x 0 80 1 00 0 0 00 x l nc l 1 82 1 00 0 0 01 x l h nc 2 84 1 00 0 0 10 x l nc nc 3 86 1 00 0 0 11 x l nc h 4 88 1 00 0 1 00 x l l l 5 8a 1 00 0 1 01 x l h h 6 8c 1 00 0 1 10 x l l nc 7 8e 1 00 0 1 11 x l l h 8 90 1 00 1 0 00 x nc nc l 9 92 1 00 1 0 01 x nc h nc 10 94 1 0 0 1 0 1 0 x nc nc nc 11 96 1 0 0 1 0 1 1 x nc nc h 12 98 1 0 0 1 1 0 0 x nc l l 13 9a 1001101x nc h h 14 9c 1001110x nc l nc 15 9e 1 0 0 1 1 1 1 x nc l h 16 a0 1010000x h nc l 17 a2 1010001x h h nc 18 a4 1010010x h nc nc 19 a6 1010011x h nc h 20 a8 1010100x h l l 21 aa 1010101x h h h 22 ac 1010110x h l nc 23 ae 1010111x h l h 24 b0 1011000x h h l 25 b2 1011001x l h l 26 b4 1011010x nc h l users follow the write byte protocol exactly, the new data contained in the data byte is written into the register selected by bits r1 and r0 on the stop bit. general purpose input/outputs (gpios) the ltc4306 provides two general purpose input/output pins (gpios) that can be configured as logic inputs, open- drain outputs or push-pull outputs. the gpio1 and gpio2 mode configure bits in register 2 determine whether the gpios are used as inputs or outputs. when the gpios are used as outputs, the gpio1 and gpio2 output mode configure bits of register 2 configure the gpio outputs either as open-drain n-channel mosfet pull-downs or push-pull stages. in push-pull mode, at v cc = 3.3v, the typical pull-up impedance is 670 ? and the typical pull-down impedance
ltc4306 4306f 14 operatio u is 35 ? , making the gpio pull-downs capable of driving leds. at v cc = 5v, the typical pull-up impedance is 320 ? and the typical pull-down impedance is 20 ? . in open- drain output mode, the user provides the logic high by connecting a pull-up resistor between the gpio pin and an external supply voltage. the external supply voltage can range from 1.5v to 5.5v independent of the v cc voltage. in input mode, the gpio input threshold voltage is 1v. the gpio1 and gpio2 logic state bits in register 1 indicate the logic state of the two gpio pins. the logic- level threshold voltage for each pin is 1v. the gpio1 and gpio2 output driver state bits in register 1 indicate the logic state that the ltc4306 is attempting to write to the gpio pins. this is useful when the gpios are being used figure 4. protocols accepted by ltc4306 figure 3. data transfer over i 2 c or smbus scl sda start condition stop condition address r/w ack data ack data ack 1-7 8 9 4306 f03 a6-a0 d7-d0 d7-d0 1-7 8 9 1-7 8 9 p s 4306 f04 s 0001 100 rd device address 1 1 71 8 1 p 1 start ack 10 a4-a0 wr xxxxxx r1r0 1 1 71 8 s 00 ack 1 s 0 ack s 0 ack m 1 register slave address start ack 10 a4-a0 rd d7-d0 1 1 71 8 s 10 data byte 1 m 1 stop 1 slave address ack start ack 10 a4-a0 wr xxxxxx r1r0 1 1 71 8 s 00 ack 1 s 0 register slave address d7-d0 8 data byte 1 s 0 stop 1 ack write byte protocol read byte protocol alert response address protocol 1 in open-drain output mode and one or more external devices are connected to the gpios. if the ltc4306 is trying to write a high to a gpio pin, but the pins actual logic state is low, then the ltc4306 knows that the low is being forced by an external device. glitch filters the ltc4306 provides glitch filters on the sdain and sclin pins as required by the i 2 c fast mode (400khz) specification. the filters prevent signals of up to 50ns (minimum) time duration and rail-to-rail voltage magnitude from passing into the two-wire bus digital interface circuitry.
ltc4306 15 4306f design example a typical ltc4306 application circuit is shown in figure 5. the circuit illustrates the level-shifting, multiplexer/switch and capacitance buffering features of the ltc4306. in this application, the ltc4306 v cc voltage and downstream bus 1 are powered from a 3.3v supply voltage; down- stream bus 4 is powered from 5v, and the upstream bus is powered from 2.5v. channels 2 and 3 are omitted for simplicity. the following sections describe a methodology for choosing the external components in figure 5. sda, scl pull-up resistor selection the pull-up resistors on the sda and scl pins must be strong enough to provide a minimum of 100 a pull-up current, per the smbus specification. in most systems, the required minimum strength of the pull-up resistors is determined by the minimum slew requirement to guaran- tee that the ltc4306s rise time accelerators are activated during rising edges. at the same time, the pull-up value should be kept low to maximize the logic low noise margin and minimize the offset voltage of the upstream-down- stream buffer circuitry. the ltc4306 is designed to func- tion for a maximum dc pull-up current of 4ma. if multiple downstream channels are active at the same time, this means that the sum total of the pull-up currents from these channels must be less than 4ma. at supply voltages of 2.7v and 5.5v, pull-up resistor values of 10k work well for capacitive loads up to 215pf and 420pf, respectively. for larger bus capacitances, refer to equation (1) below. the ltc4306 works with capacitive loads up to 2nf. applicatio s i for atio wu uu figure 5. a level shifting circuit fall time control per the i 2 c fast mode (400khz) specification, the two- wire bus digital interface circuitry provides fall time con- trol when forcing logic lows onto the sdain bus. the fall time always meets the limits: (20 + 0.1 ? c b ) < t f < 300ns v cc c1 0.01 f v cc = v bus1 = 3.3v v back = 2.5v v cc v bus4 = 5v r4 10k r7 10k r8 10k r9 10k r5 10k r6 10k 6 ltc4306ufd gpio1 d1 address = 1000 100 address = 1111 001 address = 1111 000 scl1 sda1 alert1 sclin sda1n alert 16 17 18 15 14 7 12 11 10 3 4 2 1 8 scl4 sda4 alert4 adr2 adr1 adr0 gnd sfp module 1 microcontroller r3 10k r2 10k r10 1k r1 10k sfp module 4 4306 f05 operatio u where t f is the fall time in ns and c b is the equivalent bus capacitance in pf. whenever the upstream-downstream buffer circuitry is active, its output signal will meet the fall time requirements, provided that its input signal meets the fall time requirements.
ltc4306 4306f 16 assume in figure 5 that the total parasitic bus capacitance on sda1 due to trace and device capacitance is 100pf. to ensure that the boost currents are active during rising edges, the pull-up resistor must be strong enough to cause the sda1 pin voltage to rise at a rate of 0.8v/ s as the pin voltage is rising above 0.8v. the equation is: rk vv ns v pull up max busmin ? ? [] = ? ? ? , (C.)? 0 8 1250 ?? ? ? ? ? ? ? ? ? [] cpf bus (1) where v busmin is the minimum operating pull-up supply voltage, and c bus is the bus parasitic capacitance. in our example, v bus1 = v cc = 3.3v, and assuming 10% supply tolerance, v bus1min = 2.97v. with c bus = 100pf, r pull-up,max = 27.1k. therefore, we must choose a pull- up resistor smaller (i.e., stronger pull-up) than 27.1k, so a 10k resistor works fine. alert, ready and gpio component selection the pull-up resistors on the alert and ready pins must provide a maximum pull-up current of 3ma, so that the ltc4306 is capable of holding the pin at logic low voltages below 0.4v. when choosing leds to be driven by the ltc4306s gpio pins, make sure that the required led sinking current is less than 5ma, and add a current- limiting resistor in series with the led. level shifting considerations in the design example of figure 5, the ltc4306 v cc voltage is less than or equal to both of the downstream bus pull-up voltages, so buses 1 and 4 can be active at the same time. likewise, the rise time accelerators can be turned on for the downstream buses, but must never be activated on sclin and sdain, because doing so would result in significant current flow from v cc to v back during rising edges. other application circuits figure 6 illustrates how the ltc4306 can be used to expand the number of devices in a system by using nested addressing. each i/o card contains a temperature sensor having device address 1001 000. if the four i/o cards were plugged directly into the backplane, the four sensors would require four unique addresses. however, if masters use the ltc4306 in multiplexer mode, where only one downstream channel is connected at a time, then each i/o card can have a device with address 1001 000 and no problems will occur. figures 7 and 8 show two different methods for hot- swapping i/o cards onto a live two-wire bus using the ltc4306. the circuitry of figure 7 consists of an ltc4306 residing on the edge of an i/o card having four separate downstream buses. connect a 200k resistor to ground from the enable pin and make the enable pin the shortest pin on the connector, so that the enable pin remains at a constant logic low while all other pins are connecting. this ensures that the ltc4306 remains in its default high impedance state and ignores connection transients on its sdain and sclin pins until they have established solid contact with the backplane 2-wire bus. in addition, make sure that the alert connector pin is shorter than the v cc pin, so that v cc establishes solid contact with the i/o card pull-up supply pin and powers the pull-up resistors on alert1Calert4 before alert makes contact. figure 8 illustrates an alternate sda and scl hot-swap- ping technique, where the ltc4306 is located on the backplane and an i/o card plugs into downstream channel 4. before plugging and unplugging the i/o card, make sure that channel 4s downstream switch is open, so that it does not disturb any 2-wire transaction that may be occurring at the moment of connection/disconnection. note that pull-up resistor, r17, on alert4 should be located on the backplane and not the i/o card to ensure proper operation of the ltc4306 when the i/o card is not present. the pull- up resistors on scl4 and sda4, r15 and r16 respec- tively, may be located on the i/o card, provided that downstream bus 4 is never activated when the i/o card is not present. otherwise, locate r15 and r16 on the backplane. applicatio s i for atio wu uu
ltc4306 17 4306f applicatio s i for atio wu uu figure 6. nested addressing application v cc p temperature sensor temperature sensor temperature sensor v cc r6 10k c1 0.01 f r7 10k r8 10k r4 10k r5 10k r2 10k r3 10k r1 1k led 4 6 16 17 18 21 20 22 23 24 19 15 14 7 2 5 1 13 8 9 12 11 10 3 r9 10k r10 10k r11 10k temperature sensor r12 10k r13 10k r14 10k r15 10k r16 10k r17 10k 4306 f06 address = 1001 000 address = 1001 000 address = 1001 000 address = 1001 000 open sclin sdain enable alert ready gpi01 gpi02 adr2 adr1 adr0 gnd scl1 sda1 alert1 scl2 sda2 alert2 scl3 sda3 alert3 scl4 sda4 alert4 v cc l address = 1010 000 tc4306ufd
ltc4306 4306f 18 figure 7. hot-swapping application applicatio s i for atio wu uu c1 0.01 f 4 16 6 17 18 21 20 22 23 24 19 15 14 7 13 8 9 2 5 1 12 11 10 3 led backplane connector card connector r2 10k r15 10k r16 10k r17 10k r1 1k r12 10k r13 10k r14 10k r9 10k r10 10k r11 10k r6 10k r7 10k r8 10k v cc r4 10k r5 10k v cc v cc v cc 4306 f07 card_scl1 card_sda1 card_alert1 card_scl2 card_sda2 card_alert2 card_scl3 card_sda3 card_alert3 card_scl4 card_sda4 card_alert4 r18 200k r3 10k p open sclin v bus2 sdain enable adr2 adr1 adr0 gnd scl1 sda1 scl2 sda2 scl3 sda3 scl4 sda4 v cc ltc4306ufd ready gpi01 gpi02 address = 1010 000 alert4 alert3 alert2 alert alert1
ltc4306 19 4306f information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. gn package 24-lead plastic ssop (reference ltc dwg # 05-08-1641) package descriptio u .337 C .344* (8.560 C 8.738) gn24 (ssop) 0204 12 3 4 5 6 7 8 9 10 11 12 .229 C .244 (5.817 C 6.198) .150 C .157** (3.810 C 3.988) 16 17 18 19 20 21 22 23 24 15 14 13 .016 C .050 (0.406 C 1.270) .015 .004 (0.38 0.10) 45 0 C 8 typ .0075 C .0098 (0.19 C 0.25) .0532 C .0688 (1.35 C 1.75) .008 C .012 (0.203 C 0.305) typ .004 C .0098 (0.102 C 0.249) .0250 (0.635) bsc .033 (0.838) ref .254 min recommended solder pad layout .150 C .165 .0250 bsc .0165 .0015 .045 .005 *dimension does not include mold flash. mold flash shall not exceed 0.006" (0.152mm) per side **dimension does not include interlead flash. interlead flash shall not exceed 0.010" (0.254mm) per side inches (millimeters) note: 1. controlling dimension: inches 2. dimensions are in 3. drawing not to scale ufd package 24-lead plastic qfn (4mm x 5mm) (reference ltc dwg # 05-08-1696) 4.00 0.10 (2 sides) 2.65 0.10 (2 sides) 5.00 0.10 (2 sides) note: 1. drawing proposed to be made a jedec package outline mo-220 variation (wxxx-x). 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1 top mark (note 6) 0.40 0.05 23 24 1 2 bottom viewexposed pad 3.65 0.10 (2 sides) 0.75 0.05 r = 0.115 typ pin 1 notch r = 0.30 typ 0.25 0.05 0.50 bsc 0.200 ref 0.00 C 0.05 (ufd24) qfn 0505 recommended solder pad pitch and dimensions 0.70 0.05 0.25 0.05 0.50 bsc 2.65 0.05 (2 sides) 3.65 0.05 (2 sides) 4.10 0.05 5.50 0.05 3.10 0.05 4.50 0.05 package outline
ltc4306 4306f 20 linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com ? linear technology corporation 2005 lt/lwi/tp 0805 500 ? printed in usa applicatio s i for atio wu uu related parts part number description comments ltc1380/ltc1393 single-ended 8-channel/diffierential 4-channel analog low r on : 35 ? single-ended/70 ? differential, expandable to mux with smbus interface 32 single or 16 differential channels ltc1427-50 micropower, 10-bit current output dac with smbus precision 50 a 2.5% tolerance over temperature, 4 selectable interface smbus addresses, dac powers up at zero or midscale ltc1694/ltc1694-1 smbus accelerator improved smbus/i 2 c rise time, ensures data integrity with multiple smbus/i 2 c devices lt ? 1786f smbus controlled ccfl switching regulator 1.25a, 200khz, floating or grounded lamp configurations ltc1695 smbus/i 2 c fan speed controller in thinsot tm 0.75 ? pmos 180ma regulator, 6-bit dac ltc1840 dual i 2 c fan speed controller two 100 a 8-bit dacs, two tach inputs, four gpio ltc4300a-1/ltc4300a-2 hot swappable 2-wire bus buffer isolates backplane and card capacitances ltc4300a-3 hot swappable 2-wire bus buffer provides level shifting and enable functions ltc4301 supply independent hot swappable 2-wire bus buffer supply independent ltc4301l hot swappable 2-wire bus buffer with low voltage allows bus pull-up voltages as low as 1v on sdain and sclin level translation ltc4303/ltc4304 how swappable bus buffers with stuck bus recovery recover stuck buses with automatic clocking ltc4305 2-channel 2-wire multiplexer with capacitance 2 selectable downstream buses, stuck bus disconnect, rise time buffering accelerators, fault reporting, 10kv hbm esd tolerance thinsot is a trademark of linear technology corporation. figure 8. downstream side hot-swapping application v cc = 3.3v temperature sensor v cc r6 10k c1 0.01 f r7 10k r8 10k r4 10k r5 10k r2 10k r3 10k r1 1k led micro- controller voltage monitor r9 10k r10 10k r11 10k temperature sensor r12 10k r13 10k r14 10k voltage monitor i/o card r15 10k r16 10k r17 10k 4306 f08 v cc2 = 5v v cc3 = 2.5v v cc4 = 3.3v open sclin sdain enable ready gpi01 gpi02 adr2 adr1 adr0 gnd scl1 sda1 scl2 sda2 scl3 sda3 scl4 sda4 v cc address = 1010 000 ltc4306ufd alert4 alert3 alert2 alert alert1

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